CLEAR: Cross-Layer Exploration for Architecting Resilience - Combining Hardware and Software Techniques to Tolerate Soft Errors in Processor Cores

摘要

We present a first of its kind framework which overcomes a major challenge inthe design of digital systems that are resilient to reliability failures:achieve desired resilience targets at minimal costs (energy, power, executiontime, area) by combining resilience techniques across various layers of thesystem stack (circuit, logic, architecture, software, algorithm). This is alsoreferred to as cross-layer resilience. In this paper, we focus onradiation-induced soft errors in processor cores. We address both single-eventupsets (SEUs) and single-event multiple upsets (SEMUs) in terrestrialenvironments. Our framework automatically and systematically explores the largespace of comprehensive resilience techniques and their combinations acrossvarious layers of the system stack (586 cross-layer combinations in thispaper), derives cost-effective solutions that achieve resilience targets atminimal costs, and provides guidelines for the design of new resiliencetechniques. We demonstrate the practicality and effectiveness of our frameworkusing two diverse designs: a simple, in-order processor core and a complex,out-of-order processor core. Our results demonstrate that a carefully optimizedcombination of circuit-level hardening, logic-level parity checking, andmicro-architectural recovery provides a highly cost-effective soft errorresilience solution for general-purpose processor cores. For example, a 50ximprovement in silent data corruption rate is achieved at only 2.1% energy costfor an out-of-order core (6.1% for an in-order core) with no speed impact.However, selective circuit-level hardening alone, guided by a thorough analysisof the effects of soft errors on application benchmarks, provides acost-effective soft error resilience solution as well (with ~1% additionalenergy cost for a 50x improvement in silent data corruption rate).